![]() If using a hierarchical design, the other files must be added. The high-level ARCHITECTURE is defined in the file counter7segment.vhd. It has an ARCHITECTURE block with two components (counter & leddcd). It should be noted that the example used in this tutorial is a hierarchical design. Xilinx Project Navigator will load your design and the windows will look something similar to what is illustrated below. Make sure VHDL Module is highlighted and press OK. You may be asked to clarify what is the source via the Choose Source Type window. ![]() Note if you are using a hierarchical design, enter the high level module first. Now enter your source code through the Add Existing Sources window by highlighting the desired source code and pressing Open. Using the pull-down menu (or alternatively the right mouse click) select Project > Add Source. In the Sources in Project window, left click on the line where XC2s50 5tq144-XST VHDL (or XC2s50 6tq144-XST) is located to highlight that entry. Next you need to add your source code to the project. At this point you should make sure your already compiled and simulated VHDL source code is located in the directory you created in step 3. After starting the Xilinx Project Navigator, the following screen will be displayed: 1ģ 5. ![]() To Start the Xilinx Project Navigator, Start > Engineering Applications > Xilinx ISE 5 > Project Navigator or using the following icon: 2. Assumption: Students have a basic understanding of Windows Procedures: 1. Finally, although the downloading utility is NOT apart of the Xilinx Project Navigator, the steps to download the design are also provided here. Generate a bit stream so the design can be downloaded onto the Spartan II FPGA residing on the XESS XSA-50 FPGA protoboard. Sendek Xilinx Project Navigator Reference Guide Background: This guide provides you with step-by-step procedures in using the Xilinx Project Navigator to perform the following: Synthesize your Very High speed Integrated Circuit Hardware Description Language (VHDL) code to a netlist Map, place and route your netlist onto a Spartan II FPGA (which is used on the XESS XSA-50 Field Programmable Gate Array (FPGA) protoboard Map Input/Output (I/O) pins to devices on the XESS XSA-50 FPGA protoboard. ![]()
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